RISC-V Reaches a Turning Point

RISC-V, introduced in 2010, is the first novel instruction set architecture (ISA) to gain market traction in decades. New design firms such as SiFive — founded by the credited inventors of RISC-V at the University of California, Berkeley — as well as Ventana, lowRISC and FOSSi were built around this ISA, but many Arm licensees, such as Renesas and Qualcomm, are joining them, adding RISC-V designs to their product portfolios.

RISC-V largely started in embedded and Internet of things (IoT) applications, scaling up to uses in smartphones and single-board computers. There’s been significant investment toward using the ISA for artificial intelligence (AI) and machine learning workload accelerators and as a fully fledged competitor to CPUs for data centres.

Production readiness was the prevailing theme at the fifth annual RISC-V Summit in December 2022. Several firms praised the open-source, royalty-free ISA and showcased core designs available under licence for inclusion in a custom chip or as a finished chip ready for integration in a larger product.

Qualcomm Touts Shipment of 650 Million RISC-V Cores

Qualcomm, known for its Arm-based Snapdragon chips used in smartphones, tablets and notebook PCs, boasted its adoption of RISC-V, saying it has shipped 650 million RISC-V cores for mobile, automotive, extended reality and IoT solutions. The chipmaker uses the ISA for microcontrollers in its Snapdragon range.

It isn’t surprising to see Qualcomm, a founding member of RISC-V International, publicly discuss its adoption of the ISA. However, since shipping its first RISC-V microprocessor core in the Snapdragon 865 in 2019, relations have soured with Arm following the latter’s failed takeover by Nvidia and a lawsuit concerning licensing terms after Qualcomm’s purchase of Nuvia.

At the RISC-V Summit, Qualcomm’s director of product management Manju Varma highlighted the customization support, fit for need and small code size of RISC-V, saying that “the existing legacy architecture didn’t meet these requirements”, without naming that architecture.

Ventana Aims for Enterprise with Veyron V1

Ventana Micro Systems, a semiconductor design start-up led by CEO Balaji Baktha and chief architect Greg Favor, provided more detail on the Veyron V1 core chiplet it previewed in September 2021. The new product, targeted at cloud and enterprise applications, integrates 16 “high performance” RISC-V cores as a eight-wide superscalar out-of-order design. These cores run at 3.6 GHz and are paired with a shared 48 MB L3 cache.

Ventana notes that its design is portable across foundries and process nodes — the design is available for TSMC’s 5 nm and 3 nm processes, and other components, such as PCIe and high-bandwidth memory, can be manufactured on lower-cost, mature nodes in comparatively lower demand. Notably, Ventana is not selling a ready-made system-on-chip (SoC) — this is only a chiplet. The company presents its approach as a flexible turnkey solution. Some start-ups in the AI and machine learning accelerator market use RISC-V under the hood; these initiatives could combine their intellectual property with Ventana’s RISC-V chiplet in a fully fledged SoC.

SiFive and Intel Demonstrate Horse Creek Developer Board

Accessible and affordable development hardware is integral to the success of a platform, and RISC-V is no exception. SiFive has produced developer boards in the past, starting with HiFive Unleashed in 2018. At the RISC-V Summit, further information about the newest development platform, Horse Ridge, was revealed.

Notably, Intel has partnered with SiFive to build the leading-edge reference board, as it courts RISC-V players as target customers for foundry services. Horse Creek is equipped with a quad-core SiFive P550 processor clocked at 2.2 GHz, with 8GB of DDR5-5600 RAM soldered on-board and eight lanes of PCIe 5.0 connectivity. The CPU was fabricated using the Intel 4 (7 nm) process. Support for Ubuntu 20.0 on Linux 5.17.4 was previously demonstrated at Intel Innovation 2022.

Horse Creek is intended more for rapid prototyping for enterprise and edge computing than as a general-purpose software development board or single-board computer like Raspberry Pi. Pricing information hasn’t yet been disclosed.


Growing momentum for RISC-V could signal a shift in client and enterprise computing. Hardware designers will have more options, with ready-to-use RISC-V SoCs and pre-built intellectual property blocks for integration in a larger, custom-designed SoC. But the main benefits of RISC-V are in licensing and adoption — achieving and sustaining critical mass is key to surpassing the trajectories that forerunners such as MIPS and SPARC have had in the market.

From a software standpoint, the role that RISC-V plays alongside existing x86-64 and Arm options requires further investment. To some extent, the proliferation of Arm in data centres has ushered in a trend of multiarchitecture development, potentially opening the door for RISC-V. Alibaba Cloud is working on porting Android to RISC-V, and Google, the maintainer of the Android Open Source Project, is actively accepting patches for a RISC-V port. Android support for RISC-V could encourage a variety of uses, such as cloud game streaming, or be used in more flexible, cheaper IoT devices.